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1024K/512K x18 SYNCHRONOUS DUAL QDR-IITM
(R)
PRELIMINARY DATASHEET IDT70P3307 IDT70P3337
Features

18Mb Density (1024K x 18) - Also available 9Mb Density (512K x 18) QDR-II x 18 Burst-of-2 Interface - Commercial: 233MHz, 250MHz Separate, Independent Read and Write Data Ports - Supports concurrent transactions Dual Echo Clock Output Two-Word Burst on all DPRAM accesses DDR (Double Data Rate) Multiplexed Address Bus - One Read and One Write request per clock cycle DDR (Double Data Rate) Data Buses - Four word burst data (Two Read and Two Write) per clock on each port

- Four word transfers per clock cycle per port (four word bursts on 2 ports) Port Enable pins (E0,E1) for depth expansion Dual Echo Clock Output with DLL-based phase alignment High Speed Transceiver Logic inputs that can be scaled to receive signals from 1.4V to 1.9V Scalable output drivers - Drives HSTL, 1.8V TTL or any voltage level from 1.4V to 1.9V - Output impedance adjustable from 35 ohms to 70 ohms 1.8V Core Voltage (VDD) 576-ball Flip Chip BGA (25mm x 25mm, 1.0mm ball pitch) JTAG Interface - IEEE 1149.1 Compliant
Functional Block Diagram
VREFL EP[1:0] EL[1:0]
WRITE REGISTER WRITE REGISTER
VREFR
ER[1:0]
D0 L - D1 7 L KL KL
LEFT PORT DATA REGISTER AND LOGIC
KL ZQL (1) Q0 L - Q1 7 L CQL, CQL
WRITE DRIVER
RIGHT PORT DATA REGISTER AND LOGIC
KR
SELECT OUTPUT
D0 R - D1 7 R KR KR
OUTPUT REGISTER
OUTPUT REGISTER
OUTPUT BUFFER
OUTPUT BUFFER
SELECT OUTPUT
SENSE AMPS
SENSE AMPS
ZQR (1) Q0 R - Q1 7 R CQR, CQR
MUX
KL CL
MUX
1024/512K x 18 MEMORY ARRAY
KR CR
A0L- A18L
(2)
RL WL BW0 L - BW1 L KL KL
LEFT PORT ADDRESS REGISTER AND LOGIC
OR
CL, CL KL, KL
OR
CR, CR KR, KR
ADDRESS DECODE
RIGHT PORT ADDRESS REGISTER AND LOGIC
A0R- A18R(2) RR WR BW0 R - BW1 R KR KR
TDI VREFL TDO
JTAG
TCK TMS TRST
6725 drw01
VREFR
NOTES: 1. Input pin to adjust the device outputs to the system data bus impedance. 2. Address A18 is a INC for IDT70P3337. Disabled input pin (Diode tied to VDD and VSS).
July 16, 2007
(c)2007 Integrated Device Technology, Inc. All rights reserved. Advanced Datasheet for informational purposes only. Product specifications subject to change without notice. NOT AN OFFER FOR SALE The information presented herein is subject to a Non-Disclosure Agreement (NDA) and is for planning purposes only. Nothing contained in this presentation, whether verbal or written, is intended as, or shall have the effect of, a sale or an offer for sale that creates a contractual power of acceptance. "QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semicondor, IDT, and Micron Tecnology, Inc." DSC-6725/1
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
Pin Configuration
70P3307 70P3337 RM-576 Ball Flip Chip BGA Top View
A1 BALL PAD CORNER
1 A
VSS
2
VSS INC INC INC
3
ZQR VSS VDDQR VSS
4
VSS
5
6
7
8
A3R A4R A1R VSS VDDQR VSS VDDQR
9
RR A5R A6R VDDQR VSS VDD VSS
10
BW0R INC A7R VSS VDD VSS VDD
11
E0R E1R KR VDDQR VSS VDD VSS
12
VDD VSS KR VSS VDD VSS VDD
13
VREFR VDD CR VSS VDD VSS VDD
14
INC BW1R CR VDDQR VSS VDD VSS
15
A8R WR A10R VSS VDD VSS VDD
16
A9R A12R A11R VDDQR VSS VDD VSS
17
A14R A13R A16R VSS VDDQR VSS VDDQR
18
A15R A18R A17R VDDQR VSS VDDQR VSS
19
VDDQR VSS
20
VSS VSS
21
22
23
VSS INC INC INC INC
24 A
VSS
VSS VDDQR A2R VSS
EP0
MRST DOFFR VSS INC INC INC INC INC VDDQR VSS VDDQR VSS
B
VSS VDDQR DEPTH INC INC INC INC INC VSS
B C
INC VSS VDDQR INC A0R VDDQR VDDQR VSS VDDQR VSS VDDQR INC INC INC INC CQR Q16R Q14R Q12R Q10R Q16L Q14L Q12L INC
C D
INC VSS VDDQR INC
D E
INC INC VDDQR INC VSS VSS VDDQR INC VDDQR VSS INC VSS VDDQR INC
E F
VSS VDDQR INC VSS D26R INC
F G
VREFR INC VDDQR VSS VSS
G H
INC D8R VSS Q8R Q6R Q4R Q2R Q0R Q8L Q6L Q4L CQR VSS VDDQR VSS VSS VDDQR VSS VDDQR VDD VSS VDD VSS VDD VSS VDD VSS VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD VSS VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD VSS VSS VDD VSS VDD VSS VDD VSS VDD VDD VSS VDD VSS VDD VSS VDD VSS VSS VDDQR VSS VDDQR VSS VDDQL VSS VDDQL VDDQR VSS VDDQR VSS VDDQR VSS VDDQL VSS VSS VDDQR VSS VDDQR VSS VDDQL VSS VDDQL Q17R Q15R Q13R Q11R Q9R Q17L Q15L Q13L VDDQR VSS VSS D15R VREFR
H J
D7R D6R VDDQR D4R VSS Q7R VDDQR Q5R D16R
J K
D5R VSS VDDQR VSS VDDQR D13R VSS D11R D14R
K L
D3R D2R VDDQR D0R D8L D6L D4L Q3R VDDQR Q1R D12R
L M
D1R VSS VDDQL VSS VDDQL VSS VDDQR VSS VDDQL VSS VDDQL VSS VDDQL VSS VDD VSS VDD VDDQR D9R VSS D17L D10R
M N
D7L Q7L VDDQL Q5L VSS D16L
N P
D5L VDDQL D15L VSS D13L D14L
P R
D3L Q3L VDDQL VSS VDDQL VSS VDDQL D12L
R T
D1L D2L VSS D0L VSS VDDQL VSS Q2L Q0L INC INC INC INC INC VSS VSS Q1L VSS VSS VDDQL VSS VDDQL VSS VDDQL A1L A4L A3L VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VSS KL VDD VREFL VSS VDD VSS VDD VSS VSS CL VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDD VSS VDDQL VSS VDDQL VSS VDDQL VSS VDDQL VSS Q10L CQL INC INC INC INC VDDQL VSS TRST Q11L Q9L INC INC INC INC INC VDDQL TCK VDDQL D11L VSS VDDQL D9L VSS INC INC INC INC INC VSS D10L
T U
VREFL CQL VDDQL INC INC INC VSS INC
U V
VSS VREFL
V W
INC INC VDDQL INC VSS VDDQL VSS VSS VDDQL VSS A0L VSS VDD VSS A6L A5L RL VSS VDD VSS VDD VSS VDD VSS A11L A12L A9L VDDQL VSS VDDQL A16L A13L A14L VSS VDDQL VSS A17L A18L A15L VDDQL VSS VDDQL VSS VDDQL VSS VSS VDDQL VSS VDDQL DOFFL TDO VSS
W Y
INC INC
Y AA
INC INC VDDQL INC INC VSS VSS VDDQL ZQL INC VDDQL VDDQL VSS TDI TMS VDDQL VDDQL A7L INC BW0L KL E1L E0L VDDQL VDDQL CL BW1L INC A10L WL A8L INC
AA AB
INC
AB
INC
AC
VSS VDDQL EP1 VSS A2L VSS VDD VSS
AC AD
VSS VSS
AD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
6725 drw02
NOTE: 1. The package is 25mm x 25mm x 2.55mm with 1.0mm ball pitch; the customer will have to provide external airflow of 100LFM (0.5m/s) or higher at 250MHz.
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July 16, 2007
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
Functional Description
As a memory standard, the (Quad Data Rate) QDR-II SRAM interface has become increasingly common in high performance networking systems. With the QDR-II interface/configuration, memory throughput is increased without increasing the clock rate via the use of two unidirectional buses on each of providing 2 ports of QDR-II makes this a Dual-QDRII Static Ram two ports to transfer data without the need for bus turnaround. Dual QDR-II Static RAMs are high speed synchronous memories supporting two independent double-data-rate (DDR) read and write data ports. This scheme allows simultaneous read and write access for the maximum device throughput - two data items are passed with each read or write. Four data word transfers occur per clock cycle, providing quad-data-rate (QDR) performance on each port. Comparing this with standard SRAM common I/O single data rate (SDR) devices, a four to one increase in data access is achieved at equivalent clock speeds. IDT70P3307/70P3337 Dual QDR-II Static RAM devices, are capable of sustaining full bandwidth on both the input and output buses simultaneously. Using independent buses for read and write data access simplifies design by eliminating the need for bidirectional buses. And all data are in two word bursts, with addressing capability to the burst level. Devices with QDR-II interfaces include network processor units (NPUs) and field programmable gate arrays (FPGAs). IDT70P3307/70P3337 Dual QDR-II Static RAMs support unidirectional 18-bit read and write interfaces. These data inputs and outputs operate simultaneously, thus eliminating the need for highspeed bus turnarounds (i.e. no dead cycles are present). Access to each port is accomplished using a common 18-bit address bus (17 bits for IDT70P3337). Addresses for reads and writes are latched on rising edges of the K and K input clocks, respectively. The K and K clocks are offset by 90 degrees or half a clock cycle. Each address location is associated with two 18-bit data words that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of the K and K clocks, memory bandwidth is maximized while simplifying overall design through the elimination of bus turnaround(s). IDT70P3307/70P3337 QDR-II DualPort Static RAMs can support devices in a multi-drop configuration (i.e. multiple devices connected to the same interface). Through this capability, system designers can support compatible devices such as NPUs and FPGAs on the same bus at the same time. Using independent ports for read and write access simplifies design by eliminating the need for bidirectional buses. All buses associated with QDR-II Dual-Port Static RAMs are unidirectional and can be optimized for signal integrity at very high bus speeds. The QDR-II Dual-Port Static RAM has scalable output impedance on its data output bus and echo clocks allowing the user to tune the bus for low noise and high performance. IDT70P3307/70P3337 Dual QDR-II Static RAMs have a single DDR address bus per port with multiplexed read and write addresses. All read addresses are received on the first half of the clock cycle and all write addresses are received on the second half of the clock cycle. The byte write signals are received on both halves of the clock cycle simultaneously with the data they are controlling on the data input bus. The Dual QDR-II Static RAM device has echo clocks, which provide the user with a clock that is precisely timed to the data output
3
and tuned with matching impedance and signal quality. The user can use the echo clock for downstream clocking of the data. For the user, echo clocks eliminate the need to produce alternate clocks with precise timing, positioning, and signal qualities to guarantee data capture. Since the echo clocks are generated by the same source that drives the data output, the relationship to the data is NOT significantly affected by external parameters such as voltage, temperature, and process as would be the case if the clock were generated by an outside source. Thus the echo clocks are guaranteed to be synchronized with the data. All interfaces of Dual QDR-II Static RAMs are HSTL, allowing speeds beyond SRAM devices that use any form of TTL interface. The interface can be scaled to higher voltages (up to 1.9V) to interface with 1.8V systems, if necessary. The device has VDDQ pins and a separate Vref, allowing the user to designate the interface operational voltage independent of the device core voltage of 1.8V VDD. Output impedance control pins allow the user to adjust the drive strength to adapt to a wide range of loads and transmission lines. Clocking The IDT70P3307/70P3337 has two sets of input clocks for both the input and output, the K, K clocks and the C, C clocks. In addition, the IDT70P3307/70P3337 has an output "echo" clock pair, CQ and CQ. The K and K clocks are the primary device input clocks. The K clock is used to clock in the control signals (R, W, E[1:0], BW0-1), the read address, and the first word of the data burst (D[17:0]) during a write operation. The K clock is used to clock in the control signals (BW0-1, E[1:0]), write address and the second word of the data burst during a write operation (D[17:0]). In the event that the user disables the C and C clocks, the K and K clocks will also be used to clock the data out of the output register and generate the echo clocks. The K and K, C and C,CQ and CQ, pairs are offset by half a clock cycle from each other. The C and C clocks may be used to clock the data out of the output register during read operations and to generate the echo clocks. C and C must be presented to the memory within the timing tolerances as shown in the AC Electrical Characteristics Table (Page 12). The output data from the IDT70P3307/70P3337 will be closely aligned to the C and C input, through the use of an internal DLL. When C is presented to the IDT70P3307/70P3337 the DLL will have already internally clocked the data to arrive at the device output simultaneously with the arrival of the C clock. The C and second data item of the burst will also correspond. Single Clock Mode The IDT70P3307/70P3337 may be operated with a single clock pair. C and C may be disabled by tying both signals high, forcing the outputs and echo clocks to be controlled instead by the K and K clocks. DLL Operation The DLL in the output structure of the IDT70P3307/70P3337 can be used to closely align the incoming clocks C and C with the
July 16, 2007
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
output of the data, generating very tight tolerances between the two. The user may disable the DLL by holding DOFF low. With the DLL off, the C and C (or K and K, if C and C are not used) will directly clock the output register of the IDT70P3307/70P3337. With the DLL off, there will be a propagation delay from the time the clock enters the device until the data appears at the output. QDR-II becomes QDRITM with DLL off. First data out is referenced to C instead of C. Echo Clock The echo clocks, CQ and CQ, are generated by the C and C clocks (or K, K if C, C are disabled). The rising edge of C generates the rising edge of CQ, and the falling edge of CQ. The rising edge of C generates the rising edge of CQ and the falling edge of CQ. This scheme improves the correlation of the rising and falling edges of the echo clock and will improve the duty cycle of the individual signals. The echo clock is very closely aligned with the data, guaranteeing that the echo clock will remain closely correlated with the data, within the tolerances designated. Normal QDR-II Read and Write Operations The IDT70P3307/70P3337 Dual QDR-II Static RAM supports QDR-II burst-of-two read/write operations. Read operations are initiated by holding the read port select (R) low, and presenting the read address to the address port during the rising edge of K which will latch the address. Data is delivered after the next rising edge of the next K (t + 1), using C and C as the output timing references; or K and K, if C and C are tied high. The write operation is a standard QDR-II burst-of-two write operation, except the data is not available to be read until the next
clock cycle (this is one cycle later than standard QDR-II SRAM). Normal QDR write cycles are initiated by holding the write port select (W) low at K rising edge. Also, the Byte Write inputs (BW0-1), designating which bytes are to be written, need to be held low for both the K and K clocks. On the rising edge of K the first word of the data must also be present on the data input bus D[17:0] observing the designated set up times. Upon the rising edge of K the first word of the burst will be latched into the input register. After K has risen, and the designated hold times observed, the second half of the clock cycle is initiated by presenting the write address to the address bus A[X:0], the BW0-1 inputs for the second data word of the burst, and the second data item of the burst to the data bus D[17:0]. Upon the rising edge of K, the second word of the burst will be latched, along with the designated address. Both the first and second words of the burst will be written into memory as designated by the address and byte write enables. The addresses for the write cycles is provided at the K rising edge, and data is expected at the rising edge of K and K, beginning at the same K that initiated the cycle. Programmable Impedance An external resistor, RQ, must be connected between the ZQ pin on the IDT70P3307/70P3337 and tied to VSS to allow the IDT70P3307/70P3337 to adjust its output drive impedance. The value of RQ must be 5X the value of the intended drive impedance of the IDT70P3307/70P3337. The allowable range of RQ to guarantee impedance matching with a tolerance of +/- 15% is 175 ohms to 350 ohms. The output impedance is adjusted every 1024 clock cycles to correct for drifts in supply voltage and temperature. If the user wishes to drive the output impedance of the IDT70P3307/70P3337 to its lowest value, the ZQ pin may be tied to VDDQ.
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July 16, 2007
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
Pin Definitions
andSymbol(1)
Pin Function Input Synchronous Input Synchronous Input Synchronous Output Synchronous Input Synchronous Input Synchronous Input Clock Input Clock Input Clock Input Clock Output Clock
Description Data input signals, sampled on the rising edge of K and K clocks during valid write operations Byte Write Selects active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks during write operations. Used to select which byte is written into the device during the current portion of the write operations. Bytes not written remain unaltered. All byte writes are sampled on the same edge as the data. Deselecting a Byte Write Select will cause the corresponding byte of data to be ignored and not written in to the device. BW0 controls D[8:0], BW1 controls D[17:9]. Address Inputs. Read addresses are sampled on the rising edge of K clock during active read operations. Write addresses are sampled on the rising edge of K clock during active write operations. These address inputs are multiplxed, so that both a read and write operation can occur on the same clock cycle. These inputs are ignored when the appropriate port is deselected. Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is deselected, Q[17:0] are automatically tri-stated. Write Control Logic, active LOW. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation in initiated. Deasserting will deselect the Write port. Deselecting the Write port will cause D[17:0] to be ignored. Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a Read operation is initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to complete and the output drivers are automatically tri-stated following the next rising edge of the C clock. (DOFFX = 1). Each read access consists of a burst of two sequential transfers. Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used together to deskew the flight times of various devices on the board back to the controller. See application example for further details. Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device. Drives out data through Q[17:0] when in single clock mode. All accesses are initiated on the rising edge of K. Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device. Drives out data through Q[17:0] when in single clock mode. Synchronous Echo clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free running and does not stop when the output data is tri-stated. Synchronous Echo Clock output. The rising edge of CQ is tightly matched to the synchronous data outputs and can be used as a data valid indication. CQ is free running and does not stop wehen the output data is tri-stated. Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[17:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be connected directly to V DDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected. EP[1:0] are used to program the Port Enable pins E[1:0]. EP[1:0] are programmed by tying the pins high or low on the board. If a customer does not want to use Pins EP[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Two Port Enable pins E[1:0] are provided to connect to the two MSB bits on the memory controller in order to cascade up to four IDT70P3307 devices. If a customer does not want to use Pins E[1:0], then these pins should be tied low. Refer to Truth Table III for Port Enable pins. Also refer to Figure 1 showing cascade/multi-drop using port-enable (E[1:0]) pins. E[1:0] are sampled on the rising edge of K for read operations and again on rising edge of K for write operations. DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the DLL turned off will be different from those listed in this data sheet. There will be an increased propagation delay from the incidence of C and C to Q, or K and K to Q as configured. Master Reset pin. When held low will reset the device. The DEPTH pin selects between the 18Mb and the 9Mb density, and it needs to be tied to V DEPTH = VDD puts the device in a 9Mb configuration. TDO pin for JTAG. TCK pin for JTAG. TDI pin for JTAG. TMS pin for JTAG. Reset pin for JTAG. Should be tied to VCC or VSS only, or can be left as a floating pin.
DD or
D[17:0]X
BW0X, BW1X
A[18:0]X(2)
Q[17:0]X WX
RX
CX CX KX KX CQX
CQX ZQX
Output Clock Input
EP[1:0] EX[1:0]
Input Input Syncronous
DOFFX MRST
Input Input Asynchronous Input Output Input Input Input Input Asynchronous
DEPTH TDO TCK TDI TMS TRST INC VREFX VDD VSS VDDQX
Vss. DEPTH = Vss puts the device in the 18Mb configuration, and
Input Reference Power Supply Ground Power Supply
Reference Voltage input. Static input used to set the reference level for HSTL inputs as well as AC measurement points. Power supply inputs to the core of the device. Should be connected to a 1.8V power supply. Ground for the device. Should be connected to ground of the system. Power supply for the outputs of the device. Should be connected to a 1.5V power supply for HSTL or scaled to the desired output voltage.
6725 tbl01
NOTES: 1. "X" = "L" for the Left Port pins and "X" = "R" for the Right Port pins. 2. A[17:0]x for IDT70P3337.
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July 16, 2007
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
Truth Table I - Synchronous Port Control(1)
D(3,4) K Stopped Stopped H H K R X W X EO(2) X X X X X X F F X X X X L X T X X L X T E1(2) X X X X X X F F T X X T DIN at K(t) DIN at K(t) X X X X X X DOUT at C (t+1) X X High - Z High - Z X X High - Z High - Z D(A+0) X X D(A+1) C Stopped Stopped High - Z High - Z C Q(A+0) Previous state Q(3,4) Q(A+1) OPERATION Clock stopped Previous state Clock stopped No operation No operation No operation No operation No operation No operation Read DOUT at C (t+2) Read Write Write
6725 tbl 03
NOTES: 1. x = "Don't Care", H = Logic High, L = Logic Low, represents rising edge. 2. T (True) = E and EP have some polarity (device selected) on the rising edge of the appropriate clock. F (False) =E and EP have opposite polarity (device de-selected) on the rising edge of the appropriate clock. See Truth Table III. 3. "A" represents address location latched by the device when operation was initiated. A+0, A+1 represents the internal address sequence in the burst. 4. "t" represents the cycle at which a read/write operation is started. t+1 and t+2 are the first and second clock cycles respectively following clock cycle t.
Truth Table II - Write Port Enable Control(2,3)
K K BW0(1) Input H H L L H H L L BW1(1) Input H H H H L L L L Write function disabled all bytes Write function disabled all bytes Write data inputs to Byte 0 Only Write data inputs to Byte 0 Only Write data inputs to Byte 1 Only Write data inputs to Byte 1 Only Write data inputs to all Bytes Write data inputs to all Bytes
6725 tbl03a
Mode
Input Input
NOTES: 1. BW0 controls D[8:0], BW1 controls D[17:9]. 2. For this table: W is Low on the rising edge of K; E0 and E1 are true on the rising edge of K. See Truth Tables I and III. Addresses for Writes are qualified on rising edge of K. 3. This table represents a subset of the potential write scenarios based upon BW0 - BW1 inputs and is meant to illustrate basic device functionality.
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July 16, 2007
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
Truth Table III - Port Enable Pins(1) Normal Read and Writes
Device Selected Bank 0 Bank 1 Bank 2 Bank 3 EP[0] VSS VDD VSS VDD EP[1] VSS VSS VDD VDD E[0] L H L H E[1] L L H H
6725 tbl05
NOTES: 1. EP [1:0] - Port Enable Programming Polarity (see pin description for the entire device). 2. Ex[1:0] - Port Enable (see pin description assigned for each port).
Cascade/Multi-Drop using Port Enable (E0 & E1) Pins
As shown below in Figure 1 four devices can be cascaded using the Port Enable (E0,E1) pins scheme. The port enable pins are subject to the same DC characteristics as the QDR interface. Refer to Pin Definitions table for pin descriptions. This diagram illustrates one port of a QDR-II dual port
Figure 1. Multi-drop Cascading using the Chip Enable E[1:0] Pins
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July 16, 2007
18/9Mb QDR-IITM x18 IDT70P3307/70P3337 SYNCHRONOUS Dual QDR-IITM
Preliminary Datasheet Commercial Temperatue Range
Absolute Maximum Ratings(1,2,3)
Symbol VDD VDDQ VTERM TBIAS TSTG IOUT Rating Supply Voltage on VDD with Respect to GND Supply Voltage on VDDQ with Respect to GND Voltage on Input, Output and I/O terminals with respect to GND Temperature Under Bias Storage Temperature Continuous Current into Outputs Value -0.5 to +2.2 -0.5 to VDD -0.3 to VDD+0.3 -55 to +125 -65 to +150 + 20 Unit V V V C C mA
6725 tbl07
Capacitance
Symbol CIN CO
(TA = +25C, f = 1.0MHz)(1)
Conditions(2) VIN = 0V VOUT = 0V Max. 5 7 Unit pF pF
6725 tbl08
Parameter Input Capacitance Output Capacitance
NOTE: 1. Tested at characterization and retested after any design or process change that may affect these parameters. 2. VDD = 1.8V, VDDQ = 1.5V
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ must not exceed VDD during normal operation 3. VTerm(MAX) = minimum of VDD +0.3V and 2.2V..
Recommended DC Operating and Temperature Conditions
Symbol VDD VDDQ VSS Parameter Power Supply Voltage I/O Supply Voltage Ground Input Reference Voltage Input High Voltage Input Low Voltage Ambient Temperature (1) Min. 1.7 1.4 0 0.68 VREF+0.1 -0.3 0 Typ. 1.8 1.5 0 VDDQ/2 - - 25 Max. 1.9 1.9 0 0.95 VDDQ+0.3 VREF-0.1 +70 Unit V V V V V V
o
Thermal Resistance
Parameter Junction to Ambient Junction to Case Symbol
JA JC
VREF VIH
Typ. 12.5 0.1
Unit C/W C/W
6725 tbl10
VIL TA
c
6725 tbl09
NOTE: 1. Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site thermal impedance. TJ = TA + PD x JA.
NOTE: 1. During production testing, the case temperature equals the ambient temperature.
Recommended Operating Temperature and Supply Voltage
Ambient Temperature 0 C to +70 C
O O
Grade Commercial Industrial
GND 0V 0V
VDD 1.8V + 100mV 1.8V + 100mV
6725 tbl06
-40 C to +85 C
O O
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DC Electrical Characteristics Over the Operating Temperature and Supply Voltage (VDD = 1.8V 100mV, VDDQ = 1.4V to 1.9V, TA = 0 to 70C)
Parameter Input Leakage Current Output Leakage Current Symbol IIL IOL IDD Test Conditions VDD = Max VIN = VSS to VDDQ Output Disabled VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min VDD = Max, IOUT = 0mA (outputs open), Cycle Time > tKHKH Min Device Deselected IOUT = 0mA (outputs open), f=Max, All Inputs < 0.2V or > VDD - 0.2V WEN=REN=High ZQ = 250, IOH = -(VDDQ/2)/(RQ/5) ZQ = 250, IOL = (VDDQ/2)/(RQ/5) IOH = -0.1mA IOL = 0.1mA VOUT = VDDQ/2 VOUT = VDDQ/2 250MHZ 233MHZ 250MHZ 233MHZ 250MHZ 233MHZ 250MHZ 233MHZ Min -10 -10 VDDQ/2 -0.12 VDDQ/2 -0.12 VDDQ -0.2 VSS -(IOHo-15%) (IOLo-15%) Max +10 +10 1636 1542 1432 1351 1212 1147 1007 956 VDDQ/2 +0.12 VDDQ/2 +0.12 VDDQ 0.2 -(IOHo+15%) (IOLo+15%) mA 2 mA 1 mA 1 mA 1 Unit A A Note 8 8
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Active Operating Current
2 Port Read
IDD1
2 Port Write
IDD2
Standby Current
ISB
Output High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output Impedance Control
VOH1 VOL1 VOH2 VOL2 | IOH | | IOL |
V V V V V
3,7 4,7 5 6 3 4
6725 tbl12
NOTES: 1. Operating Current is measured at 100% bus utilization on the active port. 2. Standby Current is only after all pending read and write burst operations are completed. 3. Outputs are impedance-controlled. IOHO = (VDDQ/2)/(RQ/5) = @Vout = VDDQ/2 and is guaranteed by device characterization for 175 < ZQ < 350. This parameter is tested at ZQ = 250, which gives a nominal 50 output impedance. 4. Outputs are impedance-controlled. IOLO = (VDDQ/2)/(RQ/5) = @Vout = VDDQ/2 and is guaranteed by device characterization for 175 < ZQ < 350. This parameter is tested at ZQ = 250, which gives a nominal 50 output impedance. 5. This measurement is taken to ensure that the output has the capability of pullling to the VDDQ rail, and is not intended to be used as an impedance measurement point. 6. This measurement is taken to ensure that the output has the capability of pulling to VSS, and is not intended to be used as an impedance measure point. 7. Programmable Impedance Mode. 8. 30A for JTAG input pins.
Input Electrical Characteristics Over the Operating Temperature and Supply Voltage (VDD = 1.8V 100mV, VDDQ = 1.4V to 1.9V, TA = 0 to 70C)
Parameter Input High Voltage, DC Input Low Voltage, DC Input High Voltage, AC Input Low Voltage, AC
NOTES:
Symbol VIH (DC) VIL (DC) VIH (AC) VIL (AC)
Min VREF +0.1 -0.3 VREF +0.2 -
Max VDDQ +0.3 VREF -0.1 VREF -0.2
Unit V V V V
Notes 1,2 1,3 4,5 4,5
6725 tbl 3
1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters. 2. VIH (Max) DC = VDDQ +0.3V, VIH (Max) AC = VDDQ +0.5V (pulse width < 20% tKHKH (min)). 3. VIL (MIN) DC = -0.3V, VIL (MIN) AC = -0.5V (pulse width < 20% tKHKH (min)). 4. This condition is for AC function test only, not for AC parameter test. 5. To maintain a valid level, the transitioning edge of the input must: Sustain a constant slew rate from the current AC level through the target AC level, VIL (AC) or VIH (AC) Reach at least the target AC level After the AC target level is reached, continue to maintain at least the target DC level, VIL (DC) or VIH (DC)
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Overshoot Timing
Undershoot Timing
VIL
VSS VSS -0.25V VSS -0.5V
20%
tKHKH (MIN)
5677 drw 06
AC Test Loads
VREF OUTPUT Device Under Test ZQ Z0 = 50 RQ = 250 VDDQ/2 RL = 50 VDDQ/2
AC Test Conditions
Parameter Core Power Supply Voltage Output Power Supply Voltage Input High Level Input Low Level Input Reference Level Input Rise/Fall Time
5677 drw 07
Symbol VDD VDDQ VIH VIL VREF TR/TF
Value 1.7-1.9 1.4-1.9 (VDDQ/2) +0.5 (VDDQ/2) -0.5 VDDQ/2 0.3/0.3 VDDQ/2
Unit V V V V V ns V
6725 tbl14
Output Timing Reference Level
NOTE: 1. Parameters are tested with RQ=250.
(VDDQ/2) +0.5V VDDQ/2 (VDDQ/2) -0.5V
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AC Electrical Characteristics
(VDD = 1.8V 100mV, VDDQ = 1.4V to 1.9V, TA(8) = 0 to 70C)
Commercial 250MHz Symbol Clock Parameters tKHKH tKC var tKHKL tKLKH tKHKH tKHKH tKHCH tKC lock tKC reset Average clock cycle time (K,K,C,C) Clock Phase Jitter (K,K,C,C) Clock High Time (K,K,C,C) Clock LOW Time (K,K,C,C) Clock to clock (KK,CC) Clock to clock (KK,CC) Clock to data clock (KC,KC) DLL lock time (K, C) K static to DLL reset 4.00
__
Com'l & Ind'l 233MHz
Parameter
Min.
Max.
Min.
Max.
Unit
Notes
6.30 0.20
__
4.30
__
7.20 0.20
__
ns ns ns ns ns ns ns cycles ns 2 1,5 9 9 10 10
1.60 1.60 1.80 1.80 0.00 1024 30
1.80 1.80 2.00 2.00 0.00 1024 30
__
__
__
__
__
__
1.80
__
2.00
__
__
__
Output Parameters tCHQV tCHQX tCHCQV tCHCQX tCQHQV tCQHQX tCHQZ tCHQX1 C,C HIGH to output valid C,C HIGH to output hold C,C HIGH to echo clock valid C,C HIGH to echo clock hold CQ,CQ HIGH to output valid CQ,CQ HIGH to output hold C HIGH to output High-Z C HIGH to output Low-Z
__
0.45
__
__
0.45
__
ns ns ns ns ns ns ns ns
3 3 3 3
-0.45
__
-0.45
__
0.45
__
0.45
__
-0.45
__
-0.45
__
0.30
__
0.32
__
-0.30
__
-0.32
__
0.45
__
0.45
__
3,4,5 3,4,5
-0.45
-0.45
Set-Up Times tAVKH tIVKH tDVKH Address valid to K,K rising edge Control inputs valid to K,K rising edge Date-in valid to K, K rising edge 0.35 0.35 0.35
__
0.37 0.37 0.37
__
ns ns ns
6 7
__ __
__ __
Hold Times tKHAX tKHIX tKHDX K,K rising edge to address hold K,K rising edge to control inputs hold K,K rising edge to data-in hold 0.35 0.35 0.35
__
0.37 0.37 0.37
__
ns ns ns
6 7
__
__
__
__
Port-to-Port Delay tCO Clock-to-Clock Offset 4.00
--
4.30
--
ns
6725 tbl15
NOTES: 1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No. 65 (EIA/JESD65) page. 2. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD, VDDQ and input clock are stable. 3. If C, C are tied High, K, K become the references for C, C timing parameters. 4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worst case at 0C and 1.9V tCHQZ, is a MAX parameter that is worst case at 70C and 1.7V. 5. This parameter is guaranteed by device characterization, but not production tested. 6. All address inputs must meet the specified setup and hold times for all latching clock edges. 7. 8. 9. 10. Control signals are R, W, BW0, BW1, E0, E1. During production testing, the case temperature equals TA. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60%of the cycle time (tKHKH). Clock to Clock time (tKHKH) and Clock to Clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
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Timing Waveform for Alternating Read and Write Operations(1,2)
Read 0 Write 1 Read 2 Write 3 Read 4 Write 5 NOP 6 Write 7 NOP 8 NOP 9
K
tKHKL tKLKH tKHKH tKHKH tKHKH
K
R
tIVKH tKHIX
W
tAVKH tKHAX
A
A0
A1
A2
A3
A4
A5
A7
tAVKH tKHAX
tAVKH tKHAX
tIVKH
tKHIX
tIVKH
tKHIX
BWx(3) B10
B11
B30
B31
B50
B51
B70
B71
D
D10
D11
D30
D31
D50
tDVKH tKHDX
D51
D70
D71
tDVKH tKHDX
Q
tCHQX1
Q00(4)
Q01
Q20
tCQHQV
Q21
Q40
Q41
tCHQX tKLKH tCHQV tCHQV
tCHQX
tKHKH
tCHQZ
C
tKHKL tKHKH tKHKH
C
tCHCQV tCHCQX tCQHQV tCQHQX
CQ
tCHCQV tCHCQX tCQHQV tCQHQX
CQ
5677 drw 09
NOTES: 1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH. 2. This waveform represents operation when DLL is ON. 3. To perform a valid write operation, both W and the appropriate BWX must be low. 4. Q00 refers to the output from A0, and Q01 refers to the output from the next internal address following A0.
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Preliminary Datasheet Commercial Temperatue Range
Timing Waveform of Back-to-Back Read-Write-Read to Same Address(1,2)
NOTES: 1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH. 2. This waveform represents operation when DLL is ON.. 3. To perform a valid write operation, both W and the appropriate BWX must be low. 4. ORIG Q00 represents the existing data in the memory. New Q00 represents the data written into the memory in the first cycle of the waveform.
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Timing Waveform for Left Port Write to Right Port Read(1)
0
1
2
3 tCO(2)
4
5
6
7
8
9
10
11
12
13
14
KL
tKHKH
KL
WL
Address_L
A0
A1
DINL
D00
D01
D10
D11
KR
KR
RR
Address_R
A0
A2
QR
tCHQX1
Q00
Q01
Q20
Q21
CR
tCHQV
CR
CQR CQR
5677 drw 11
NOTES: 1. Device is selected per E[0] and E[1] as defined inTruth Table III. MRST = VIH. BW0L, BW1L = VIL 2. If tco < specified minimum, data read from right port is not valid until the next KR cycle. If tco > specified minimum, data read from right port is available on the first KR cycle as shown.
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Preliminary Datasheet Commercial Temperatue Range
Timing Waveforms for DLL Operation (On/Off)(1,2)
Read 0 Write 1 Read 2 Write 3 Read 4 Write 5 NOP 6 Write 7 NOP 8 NOP 9
K
tKHKL tKLKH tKHKH tKHKH tKHKH
K
R
tIVKH tKHIX
W
tAVKH tKHAX
A
A0
A1
A2
A3
A4
A5
A7
tAVKH tKHAX
tAVKH tKHAX
tIVKH
tKHIX
tIVKH
tKHIX
BWX(3)
B10
B11
B30
B31
B50
B51
B70
B71
D
D10
D11
D30
D31
D50
tDVKH tKHDX
D51
D70
D71
tCHQV
tDVKH tKHDX
tCHQZ
Case 1: Q DLL OFF (QDRI)(5)
tCHQX1
Q00(4)
tCHQX tCHQV
Q01
tCHQX
Q20
Q21
Q40
Q41
Case 2: Q DLL ON (QDRII)
tCHQX1
Q00(4)
Q01
Q20
Q21
Q40
Q41
tCHQX tKLKH tCHQV tCHQV
tCHQX tCHQZ tKHKH
C
tKHKL tKHKH tKHKH
C
5677 drw 12
NOTES: 1. Device is selected per E[0] and E[1] as defined in Truth Table II, and MRST = VIH. 2. With DLL OFF (DOFFX < VIL) device behaves as a QDRI device. With DLL ON (DOFFX > VIH) device behaves as a QDR-II device. 3. To perform a valid write operation, both W and the appropriate BWX must be low on the rising edge of K. 4. Q00 refers to the output from A0, and Q01 refers to the output from the next internal address following A0. 5. With DLL off (DOFF = VIL) the propagation delays will be increased and the AC timing parameters will be different values from those specified in this data sheet.
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Master Reset Timing Waveform
K
MRST(1)
(5ns)
5677 drw13
NOTE: 1. MRST must be held LOW for a minimum of (5ns) after power supply is stable.
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IEEE 1149.1 Test Access Port and Boundary SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible Test Access Port (TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1149.1, the QDR-II Dual-Port Static RAM contains a TAP controller, Instruction Register, Bypass Register and ID Register. The TAP controller has a standard 16-state machine that resets internally upon power-up. It is possible to use this device without utilizing the TAP. To disable the TAP controller without interfacing with normal operation of the QDR-II Dual-Port Static RAM TCK must be tied to VSS to preclude a mid level input. TMS and TDI are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may also be tied to Vdd through a resistor. TDO should be left unconnected.
JTAG Block Diagram
TAP Controller State Diagram
1 Test Logic Reset 0 Run Test Idle 1 Select DR 0 1 Capture DR 0 Shift DR 1 1 Exit 1 DR 0 Pause DR 1 Exit 2 DR 1 1 Update DR 0 1 1 Select IR 0 Capture IR 0 Shift IR 1 1 Exit 1 IR 0 Pause IR 1 Exit 2 IR 1 Update IR 1 0 1
0
0
0
0 0
0 0
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Identification Register Definitions
Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0)
NOTE: 1. Device ID for IDT70P3337 is 0x353.
Value 0x0 0x352(1) 0x33 1 Reserved for version number
Description
Defines IDT part number (IDT70P3307) Allows unique identification of device vendor as IDT Indicates the presence of an ID register
6725 tbl16
Scan Register Sizes
Register Name Instruction (IR) Bypass (BYR) Identification (IDR) Boundary Scan (BSR) Bit Size 4 1 32 Note 1
6725 tbl17
NOTE: 1. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local IDT sales representative.
System Interface Parameters
Instruction EXTEST BYPASS IDCODE Code 0000 1111 0010 0100 Description Forces contents of the boundary scan cells onto the device outputs (1). Places the boundary scan register (BSR) between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Loads the ID register (IDR) with the vendor ID code and places the register between TDI and TDO. Places the bypass register (BYR) between TDI and TDO. Forces all device output drivers to a High-Z state except COLx & INTx outputs. Uses BYR. Forces contents of the boundary scan cells onto the device outputs. Places the bypass register (BYR) between TDI and TDO. Places the boundary scan register (BSR) between TDI and TDO. SAMPLE allows data from device inputs (2) to be captured in the boundary scan cells and shifted serially through TDO. PRELOAD allows data to be input serially into the boundary scan cells via the TDI. Several combinations are reserved. Do not use codes other than those identified above. For internal use only.
6725 tbl18
HIGHZ CLAMP SAMPLE/PRELOAD
0011 0001
RESERVED PRIVATE
0101, 0111, 1000, 1001, 1010, 1011, 1100 0110,1110,1101
NOTES: 1. Device outputs = All device outputs except TDO. 2. Device inputs = All device inputs except TDI, TMS, and TRST.
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JTAG DC Operating Conditions
Parameter Power Supply Voltage (I/P + O/P) Input High Level Input Low Level Output High Voltage (IOH = -1mA) Output Low Voltage (IOL = 1mA) Symbol VDD VIH VIL VOH VOL Min 1.7 1.3 -0.3 VDD - 0.2 VSS Typ 1.8 Max 1.9 VDD+0.3 0.5 VDD 0.2 Unit V V V V V
6725 tbl19
Note
JTAG AC Test Conditions
Parameter Input High/Low Level Input Rise/Fall Time Input and Output Timing Reference Level Symbol VIH/VIL TR/TF Value 1.8/0 1.0/1.0 VDD/2 Unit V ns V 1 Note
NOTE: 1. For outputs see AC test loads on page 10.
6725 tbl20
JTAG AC Characteristics
Parameter TCK Cycle Time TCK High Pulse Width TCK Low Pulse Width TMS Input Setup Time TMS Input Hold Time TDI Input Setup Time TDI Input Hold Time Input Setup Time Input Hold Time Clock Low to Output Valid TRST Low to Reset JTAG TRST High to TCK HIGH Symbol tCHCH tCHCL tCLCH tMVCH tCHMX tDVCH tCHDX tSVCH tCHSX tCLQV tJRST tJRSR Min 100 40 40 10 10 10 10 10 10 0 50 50 Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns
6725 tbl21
Note
JTAG Timing Diagram
TCK TMS
tCHCH tMVCH tCHMX
tCHCL
tCLCH
tDVCH
tCHDX
TDI
tSVCH
tCHSX
Outputs
tCLQV
TDO TRST
tJRST tJRSR
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Preliminary Datasheet Commercial Temperatue Range
Ordering Information
Preliminary Datasheet: Description
"PRELIMINARY" datasheets contain descriptions for products that are in early release.
Datasheet Document History
7/16/2007: Initial release of Preliminary Datasheet
(R)
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